1. Field of the Invention
The present invention relates to element substrates for recording heads, recording heads, head cartridges, and recording apparatuses. More particularly, the present invention relates to an element substrate for a head on which substrate heating resistors and drive circuits for driving the heating resistors are mounted, a recording head including the element substrate, a head cartridge including the recording head, and a recording apparatus including the recording head.
2. Description of the Related Art
Recording heads used in inkjet recording apparatuses have, as recording elements, discharge ports for discharging ink droplets and heating resistors (heaters). The heating resistors are composed of resistors or the like and are disposed in sections communicating with the discharge ports. A current is applied to the heating resistors so that the heating resistors generate heat to generate bubbles of ink vapor, whereby ink droplets are discharged from the discharge ports to record an image. Such a recording head allows many discharge ports and heating resistors to be arranged at a high density, and therefore the recording head is capable of performing high-definition recording.
FIG. 7 is a block diagram illustrating the circuit structure of a known recording head.
FIG. 8 is a schematic diagram illustrating the circuit layout of the recording head shown in FIG. 7.
To perform high-speed recording using the recording head, the number of heaters 110 that can be driven simultaneously is set as large as possible. However, there is a limit to current-supplying performance of an electric wire 107 to which a power supply voltage (VH) is applied. In addition, as the current is increased, a larger voltage drop occurs due to a parasitic resistance of the electric wire 107. Therefore, it is difficult to supply desired energy to a large number of heaters 110, and the number of heaters 110 that can be driven simultaneously is limited. Accordingly, the heaters 110 are divided into M groups (GR:1 to GR:M) and are driven at different times such that the heaters 110 in the same group are prevented from being driven simultaneously. Thus, a maximum current that is applied instantaneously is suppressed.
U.S. Pat. No. 6,520,613 describes an example of a circuit structure that drives in the above-described manner.
According to U.S. Pat. No. 6,520,613, M groups of N heaters are provided and are time-divisionally driven such that M heaters are driven at a time in a single driving block and N driving blocks are performed. Matrix driving is carried out in which the heaters are selected by a logical product of an output (DATA) from shift registers that store data for M heaters and an output (BLE) of N decoder signals. According to this structure, the circuit scale can be reduced and the occurrence of malfunction can be reduced because data is time-divisionally transmitted.
In the recording head, a data signal (DATA) corresponding to recording data and time-division control data is serially transmitted to shift registers in synchronization with a clock signal (CLK). The shift registers are divided into two types in accordance with the data corresponding thereto. More specifically, the shift registers are divided into a several-bit shift register 105a and M-bit shift registers 105b-1 to 105b-M. The data signal (DATA) includes M bits of recording data from the leading end thereof, and recording data signals corresponding to the recording data are output from M-bit latches corresponding to the M-bit shift resisters 105b-1 to 105b-M. The remaining bits of data are input to the shift register 105a and are decoded by a decoder, whereby N-bit BLE signals (block selection signals) are obtained. The N BLE signals are output at the time when a latch signal is switched to “H”. None of the N BLE signals are set to “H” simultaneously with another BLE signal, and only one BLE signal is set to “H” at a time.
In FIGS. 7 and 8, a combination of the decoder and the latch is denoted by 106. In addition, in FIGS. 7 and 8, the M-bit shift resisters 105b-1 to 105b-M corresponding to the M groups are shown in combination with the respective latches.
The heaters 110, driven by AND circuits 114 that are connected to the block selection signal line at which the BLE signal is set to “H” and to signal lines of the shift registers 105b-1 to 105b-M at which the corresponding bits of the M-bit data are set to “H”, are selected as the heaters 110 to be driven. The heaters 110 are driven by receiving a current in accordance with the selection signals output from the AND circuits 114 and a heat enable (HE) signal.
The above-described operation is repeated N times so that all of the M×N heaters can be selected. More specifically, the heaters are time-divisionally driven at N time points, M heaters being driven at each time point.
In the recording head having the above-described structure, M heaters are selected by a single block selection signal at substantially the same time. However, the M heaters are not driven at exactly the same time in practice, but are sequentially driven with time intervals of about several tens of nanoseconds.
An example of such a driving method is discussed in U.S. Pat. No. 6,243,111.
According to U.S. Pat. No. 6,243,111, the M heaters to be driven together are caused to receive the heat enable signal at slightly different times so that the current applied instantaneously is suppressed and noise can be reduced.
FIG. 9 shows a signal time chart illustrating delay control of the heat enable signal according to U.S. Pat. No. 6,243,111.
The left half of FIG. 9 shows the case in which the heat enable signal is applied without a delay to the M heaters that correspond to a single block and are selected to be driven together by the decoder. In this case, the total heater current that flows through the common electric wires is greatly changed at the rising and falling edges thereof. Therefore, large noise is generated due to the changes in the heater current. In comparison, in the right half of FIG. 9, the time at which the signal is applied to the heaters selected to be driven together by the decoder is successively delayed. In this case, the changes in the heater current that flows through common electric wires, such as a high-voltage-side (VH) electric wire and a low-voltage-side (GND) electric wire, can be reduced.
To apply the signal in the manner shown in the right half of FIG. 9, the heat enable signal for driving the heaters corresponding to the same block is controlled such that the heat enable signal is successively delayed at each group. Accordingly, malfunction of the circuits in the recording head substrate (element substrate) can be prevented and radiation noise can be reduced.
Delay circuits 111-1 to 111-M shown in FIG. 7 are used to shift the time at which the heat enable signal is applied. The delay circuits 111-1 to 111-M are provided for the respective groups and are arranged parallel to the arrangement direction of the heaters 110 and driver transistors 112. The delay circuits are provided on the electric line for transmitting the heat enable signal to the heaters in each group at positions between the groups. Accordingly, the M heaters are successively driven by the heat enable signal that is successively delayed as shown in the right half in FIG. 9. CR integrating circuits are used as the delay circuits. In each CR integrating circuit, the capacitance (C) component is a gate capacitance and a parasitic capacitance of the electric wire, and the resistance (R) component is an ON resistance of a metal-oxide silicon (MOS) transistor of a complementary metal-oxide semiconductor (CMOS) inverter included in the delay circuit and a parasitic resistance of the electric wire. The signal delay is generated using the delay (bluntness) caused at the rising edge and the falling edge of the signal pulse. Thus, the noise is reduced by the above-described method without increasing the manufacturing cost or using a special noise-reducing component or a noise-reducing design in the main body of the recording apparatus.
As described above, in the known structure, the noise can be reduced by an inexpensive method. However, according to this method, the heat enable signal is successively input to the delay circuits. Therefore, there is a possibility that the waveform of the heat enable signal will be changed in the delay circuits and the pulse width will also be changed as a result. The pulse width of the heat enable signal has an important role of defining the energy applied to the ink. Therefore, it is necessary that the heat enable signal input from the main body of the recording apparatus and the heat enable signal transmitted to the driver transistors from the circuits have the same pulse width.
In particular, in the circuit structure or the circuit layout used when the element substrate shown in FIGS. 7 and 8 has an ink supply port or when the element substrate has a long length, the electric wire for the heat enable signal has a large length. Therefore, there is a high risk that the pulse width will be changed because the signal shape is largely influenced by the parasitic load.
FIG. 10 illustrates the inner structure of the delay circuits to which the heat enable signal is input. FIGS. 11A and 11B are diagrams illustrating the manner in which the waveform of the heat enable signal is changed as the signal is transmitted through the delay circuits.
As described above, the delay circuits include CR integrating circuits for delaying the heat enable signal. The amount of delay generated by each delay circuit is determined by a capacitance C, a resistance R, and a threshold (Vth) of an inverter. The waveform of an output signal pulse output from each delay circuit is smoothed at the rising and falling edges in accordance with the capacitance and resistance, and the signal is transmitted to the next delay circuit when the smoothed pulse voltage reaches the threshold (Vth). In other words, the amount of delay is increased as the smoothness of the pulse is increased.
As shown in FIG. 10, each delay circuit includes two inverters connected in series.
More specifically, a first inverter 401 and a second inverter 402 are disposed next to each other and are connected to each other. The capacitance C for generating a delay is mainly determined by a gate of the second inverter 402, and the resistance R also for generating a delay is mainly determined by the driving performance of P-channel metal-oxide semiconductors (PMOSs) 403 or N-channel metal-oxide semiconductors (NMOSs) 404. A point at which the signal is input to the gate is shown as point B in FIG. 10. The signal waveform obtained at point B is indicated as point B in FIGS. 11A and 11B.
As is clear from the waveform at point B in FIGS. 11A and 11B, the waveform is not greatly smoothed by the capacitance and resistance because the delay circuit does not have other large loads. Therefore, the amount of delay is relatively small. Currents denoted by “a” and “b” in FIG. 10 correspond to portions denoted by “a” and “b” in the signal waveform indicated as point B in FIGS. 11A and 11B. In comparison, at the output point of the first delay circuit 111-1 that is shown as point C, the parasitic resistance and parasitic capacitance of the electric wire and a gate capacitance connected to AND circuits 405 are additionally applied. Although a plurality of AND circuits 405 are disposed between the delay circuits in each group, only one AND circuit 405 is shown for simplicity of the drawing.
Therefore, at point C, the signal waveform is further smoothed compared to that at point B, and the amount of delay is increased. This is clear from the signal waveform indicated by point C in FIGS. 11A and 11B. Currents denoted by “c” and “d” in FIG. 10 correspond to portions denoted by “c” and “d” in the signal waveform indicated as point C in FIGS. 11A and 11B.
Similarly, currents denoted by “e” and “f” in FIG. 10 correspond to portions denoted by “e” and “f” in the signal waveform indicated as point D in FIGS. 11A and 11B. In addition, currents denoted by “g” and “h” in FIG. 10 correspond to portions denoted by “g” and “h” in the signal waveform indicated as point E in FIGS. 11A and 11B.
Ideally, the threshold (Vth) of the inverters is equal to the center value of the power supply voltage (3.3 V), and the PMOSs 403 and the NMOSs 404 have exactly the same driving performance. In such a case, as shown in FIG. 11A, the amount of delay at the rising edge of the signal pulse is exactly the same as that at the falling edge. Therefore, the pulse width does not vary.
FIG. 11B shows the amount of delay of the heat enable signal obtained when the driving performance of the PMOSs 403 differs from that of the NMOSs 404. Here, the case is considered in which the PMOSs 403 have a higher driving performance than that of the NMOSs 404.
In this case, since the NMOSs 404 have a low driving performance, the falling edge of the pulse signal is smoothed, whereas the rising edge of the pulse signal is relatively sharp as compared to the falling edge because the PMOSs 403 have a high driving performance. As a result, the pulse width changes from that of the input signal. More specifically, as shown in FIG. 11B, the pulse width is successively reduced as the signal is transmitted to the downstream delay circuits. Conversely, if the NMOSs 404 have a higher driving performance than that of the PMOSs 403, the pulse width is successively increased.
To avoid such a situation, the width of each MOS (W) is designed such that the PMOSs 403 and the NMOSs 404 have the same driving performance. However, in the semiconductor substrate manufactured in practice, errors occur due to differences caused in semiconductor manufacturing processes. The errors cause deformation in the heat enable signal, which leads to variation in the pulse width. As a result, the energy applied to the heaters varies and recording defects occur.